1. Field of the Invention
The present invention relates to a semiconductor memory device which can inhibit to use the defective addresses.
2. Description of the Related Art
Recently, a memory capacity of a semiconductor memory device, particularly, a DRAM (Dynamic Random Access Memory), is substantially increased. However, the reduction of yield of the recent semiconductor memory device due to increase of the memory capacity becomes a problem. It is very difficult to fabricate perfect semiconductor memory devices and it has been known that many semiconductor memory devices fabricated contain defective cells and/or defective bit lines. In order to salvage such semiconductor memory devices containing defective cells and/or defective bit lines, a semiconductor memory device is generally provided with a redundancy mechanism. That is, a defective semiconductor memory including a defective memory cell or a memory cell which can not be used due to a defective bit line can be used as a substantially perfect semiconductor memory by replacing the defective memory cell or the memory cell including the defective bit line by a redundancy cell. With this scheme, the reduction of yield of the semiconductor memory device is improved.
However, due to the recent drastic increase of memory capacity, there are a considerable number of cases where the semiconductor memory device fabricated includes too many defective cells and/or defective bit lines to be salvaged by such redundancy mechanism. It is not preferable in view of yield to abandon all of such semiconductor memory devices as defective memory devices. In order to salvage such semiconductor memory devices and enable to ship them as perfect semiconductor memory devices, a semiconductor memory device whose defective address can be detected by an external device has been proposed in, for example, Japanese Patent Application Laid-open No. H8-102529.
FIG. 11 shows the proposed semiconductor memory device 1000 schematically. The semiconductor memory device 1000 is a DRAM of a double word-line system including main word lines and sub-word lines. The main word line is selected by a main word decoder 1001 which receives a portion of a row address and the sub-word line is selected by sub-word line decoders 1002 which receive the remaining row address.
In FIG. 11, hatched portions are a defective address, an access to which is impossible. That is, a memory cluster 1003 to which a defective cell 1004 which can not be salvaged by a redundancy mechanism belongs can not be accessed due to the presence of the defective cell 1004 and all of memory clusters to which a defective bit line 1006 which is not salvaged by the redundancy mechanism belongs, that is, one memory block 1005, can not be accessed due to the presence of the defective bit line 1006.
FIG. 12 shows a main word line drive circuit 1100 for driving respective main word line pairs MWL and MWLB contained in the main word decoder 1001, which is provided for every main word line. This main word line drive circuit 1100 is provided with a fuse 1101 as shown in FIG. 12. When this fuse 1101 is cut, all of word lines connected to the corresponding main word line pairs MWL and MWLB becomes invalid. It should be noted here that the term "invalidation" used here means not to make an access physically impossible but to merely inhibit an access thereto from an external device.
In FIG. 11, a situation is shown in which, in order to make the memory cluster to which the defective cell 1004 belongs invalid, a fuse 1007 corresponding to this memory cluster is cut and, in order to make all memory clusters (one memory block 1005) to which the defective bit line 1006 belongs, all fuses 1008 corresponding to these memory clusters are cut.
It can be read out externally of the semiconductor memory device 1000 by using a roll call test mode whether or not the fuse 1101 is cut. In the roll call test mode, it is detected by a switching of the level of the roll call signal RCX to low level whether or not the main word line is invalid.
Therefore, in order to detect a memory cluster, that is, a main word line, which is invalid, a user of the DRAM performs the roll call test immediately after a power source of the DRAM is turned on. When it is detected in this roll call test that a certain main word line is invalid, it means that a use of a memory cluster corresponding to the invalid main word line is impossible and the memory cluster is registered in a defective address table of another memory device externally of the semiconductor memory 1000 as a defective memory cluster.
According to this technique, a portion of the memory capacity of the semiconductor memory device 1000 is practically lost due to the presence of this memory cluster which can not be used. However, since the semiconductor memory device containing defectiveness which can not be salvaged by the redundancy mechanism can be shipped as an acceptable semiconductor memory, the yield is improved.
As another prior art semiconductor memory, Japanese Patent Application Laid-open No. H7-85696 discloses a technique in which a semiconductor memory device is divided to four memory blocks and, when there is no defective bit line, all of the four memory blocks are used and the semiconductor memory device is shipped as a DRAM having memory capacity of, for example, 64M bits and, when there is, for example, three of the four memory blocks having defective bit lines, the remaining memory block which has no defectiveness is used and the semiconductor memory device is shipped as a DRAM having a memory capacity which is one fourth of the original capacity, that is, 16M bits.
In the conventional semiconductor memory device 1000, however, when there is a defective bit line 1006, all memory clusters to which the defective bit line 1006 belongs, that is, one memory block becomes invalid. Therefore, a large number of memory cells can not be used due to an existence of defective bit line and the memory capacity of the semiconductor memory is substantially reduced.